NetNews Offline 2/NetNews Offline Volume 2.iso/news/comp/sys/amiga/misc-part1/9545

Internet Message Format | 1996-08-05 | 3.8 KB

Path: EU.net!sun4nl!xs4all!usenet
From: [e-mail] (Jeroen T. Vermeulen)
Newsgroups: comp.sys.amiga.advocacy,comp.sys.amiga.datacomm,comp.sys.amiga.networking,comp.sys.amiga.misc
Subject: Re: New Press Release!
Date: Sun, 24 Mar 96 16:35:08
Organization: Leiden University, Mathematics & Computer Science, The Netherlands
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References: <4hivul$[e-mail]> <4i5hlq$[e-mail]> <[e-mail]> <4ig4io$[e-mail]> <4iv3da$[e-mail]>
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In article <4iv3da$[e-mail]> [e-mail] (John  Bayko) writes:

> Technically, the 68060 is roughly equivalent to a P6/Pentium Pro,
> except for clock speed, and I can't see any reason P6 technology
> couldn't make a 68060 as fast or faster.

I'm not a hardware type, but AFAICS they simply made it too powerful at the
start.  Long pipelines are more or less a necessary evil at high clock speeds
(the P6 suffers >10 cycle hits for instructions that don't fit the pipeline
model such as segment register writes) and with long pipelines comes another
necessary evil:  Speculative execution.

At this point there's a lot of red tape to carry around, all of which must be
sorted out into a valid state if an exception or even a branch misprediction
occurs.

Two factors apparently make that hard for the 68k ISA:  Firstly, the precise
exception model (don't know much about it though) means that given an exception
in an instruction stream there is only one valid architectural state to recover
instead of just a set of requirements where the chip can pick any convenient
one.

Secondly there is the fact that any instruction can cause several exceptions (up
to four memory accesses plus some other stuff like FP exceptions I think).
In a time when CPU vendors all wanted a powerful instruction set, the x86's were
far behind in orthogonality and expressiveness of their machine language.  This
was turned into an advantage for Intel by the RISC revolution, when it became
clear that higher clock speeds and more sophisticated hardware optimizations
came within reach once the instruction set didn't make too many demands on your
chip design.

My estimation is that Motorola chose the design direction for the 060 with very
good reasons (other than obvious market considerations).  A four-stage pipeline
with low clock speeds suits the architecture a lot better.

Look at the ColdFire:  They're simplifying the instruction set to accomodate the
higher clock speeds, and I'll wager they removed a lot of exceptions, probably
by omitting the MMU and FPU.


>     Maybe Apple's support could have paid for it, but they simply
> couldn't wait. The 68060 architecture is similar to the Pentium Pro,
> not the Pentium, and so it took longer to develop than the Pentium, so
> for a while, Motorola had nothing that could be competitive. Apple
> couldn't afford to wait that long, so went for the PowerPC.

Similar in complexity, yes.  Similar in Buzzword Feature Count (branch
prediction, superscalar, out-of-order and speculative execution, L1 cache size),
yes.  In general approach, no.

BTW I realize this is a FAQ, but at least one Motorola employee told me that
they did develop an 050, but decided not to finish it.


> John Bayko (Tau).
> [e-mail]
> http://www.cs.uregina.ca/~bayko

--
============================================================================
#  Jeroen T. Vermeulen   \"How are we doing kid?"/   Yes, we use Amigas.   #
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